Logic Gate Selection Guide for Mixed-Voltage Boards: Family, Speed, and Drive Strength

Why the Function Name Tells You Almost Nothing

Two boards, same schematic: a Low Power Dual 2-Input And Gate in both. One passes EMC with margin while the other resets itself every time a relay fires. The difference between them was a single letter in the part number — the logic family, not the logic function.

Choosing between HC, HCT, LVC, AUP, or the CD4000B series is really a decision about four things: input threshold, propagation delay, drive current, and quiescent power. Get those right and the board behaves the way it was drawn. Get them wrong and you spend a week chasing an intermittent fault that the datasheet would have flagged in one line.

The Five Parameters That Pick the Family for You

Every family datasheet leads with the same five numbers. Reading them in this order keeps you out of trouble.

Family Comparison: The Numbers Side by Side

At 3.3 V, AUP is the quietest and LVC is the strongest driver. Stepping up to AHC and HC buys a wider supply window at roughly double the delay and a much higher Cpd — and Cpd is what actually drains a battery in a switching design.

Input Thresholds: Where Most Designs Quietly Fail

VIH is the first number to check. A CMOS input in the HC family wants 0.7 × Vcc, which is 3.5 V on a 5 V rail. A 3.3 V output driving it sits below that threshold in the worst case, so the gate works on the bench in July and fails on the first cold morning.

The working rule: any time a 3.3 V source meets a 5 V CMOS input, specify an HCT or AHCT part, or put an explicit translator in the path. A 2-input single supply translating AND gate solves the same problem inside a single package when two devices share one rail but not one threshold.

Propagation Delay Tracks the Supply Rail

Delay falls as Vcc rises, which is why a design that is comfortable at 3.3 V can fall apart when the same schematic is ported to a 1.8 V rail. Dynamic current is the other half of that trade, and it scales with the square of the rail.

Dropping a 5 V design to 1.8 V cuts switching power by roughly 7× at the same clock rate.

Drive Strength and Switching Speed into Real Capacitance

Edge rate is a function of output impedance and load capacitance: tr ≈ 2.2 × Rout × Cload. That single line explains most overshoot problems.

A fast LVC output driving a long trace is the classic ringing case. Fitting a 22–33 Ω series resistor at the source slows the edge just enough to damp the reflection without eating your timing budget.

Crossing a Voltage Boundary: Four Options, Ranked

Where a wired-AND bus is required, a Single 2-input And Gate (open drain) gives you the open-drain output without adding a discrete transistor and its pull-up network. The middle two options in the table are where designers get caught: both work in simulation, and both carry a condition that a scope will find for you.

Selection Matrix by Design Need

Release Checklist Before the BOM Freezes

• Confirm every input’s VIH against the worst-case VOH of whatever drives it, not the typical value.
• Check the Vcc range against the rail’s tolerance including ripple, not just the nominal voltage.
• Verify that a 5 V tolerant input applies in the state you are actually using.
• Run the timing budget at the lowest rail voltage the specification allows.
• Add up Cpd across every switching gate on a battery-powered design.
• Check output drive against real trace and fanout capacitance.
• Fit series termination on any fast net longer than a few centimeters.
• Confirm whether channel-to-channel skew matters for your bus.
• Verify ESD and latch-up ratings against the environment the board will actually see.

Standard logic is the least glamorous line on the BOM. Picking the family on the function name alone is the shortcut that puts a board back into EMC testing a second time.